LATTICE ISPPAC-CLK5610AV-01TN48I

ISPPAC-CLK5610AV-01TN48I General Description

The advanced PLL technology integrated into the ISPPAC-CLK5610AV-01TN48I ensures exceptional performance in terms of low jitter and phase noise, guaranteeing the delivery of precise and stable clock signals essential for a wide range of applications. Moreover, this IC features programmable output dividers and delay control, allowing for customization of clock outputs to suit specific system needs. Operating efficiently on a low power supply voltage, the ISPPAC-CLK5610AV-01TN48I is a power-efficient solution ideal for applications where energy consumption is a critical consideration. Its compact size and high level of integration make it a seamless fit for integration into various electronic devices, including networking equipment, communication systems, and industrial automation solutions

Features

• Four Operating Configurations
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
• 8MHz to 267MHz Input/Output Operation
• Low Output to Output Skew (<100ps)
• Low Jitter Peak-to-Peak (<70 ps)
• Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards and individual enable controls
• - LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
• - 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
• - 1.5V, 1.8V, 2.5V, 3.3V
• Fully Integrated High-Performance PLL
• Programmable lock detect
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
• Precision Programmable Phase Adjustment (Skew) Per Output
• 8 settings; minimum step size 156ps
• - Locked to VCO frequency
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
• Up to Three Clock Frequency Domains
• Flexible Clock Reference and External Feedback Inputs
• Programmable single-ended or differential input reference standards
• - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
• - LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
• All Inputs and Outputs are Hot Socket Compliant
• Full JTAG Boundary Scan Test In-System Programming Support
• Exceptional Power Supply Noise Immunity
• Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• 48-pin and 64-pin TQFP Packages

Specifications