MMC2120MG

Features

• Features of the MMC2107 include:
• MCORE M210 integer processor:
• – 32-bit reduced instruction set computer (RISC) architecture
• – Low power and high performance
• OnCE™ debug support
• On-chip 128-Kbyte FLASH:
• – Motorola’s one transistor, CDR MoneT(1) FLASH bit cell
• – Page mode (2111) read access
• – External VPP required for programming
• – 16-K block size
• On-chip, 8-Kbyte static random-access memory (SRAM):
• – One clock per access (including bytes, half-words, and words)
• – Byte, half-word (16 bits), and word (32 bits) read/write accesses
• – Standby power supply support
• Serial peripheral interface (SPI):
• – Master mode and slave mode
• – Wired-OR mode
• – Slave select output
• – Mode fault error flag with CPU interrupt capability
• – Double-buffered operation
• – Serial clock with programmable polarity and phase
• – Control of SPI operation during wait mode
• – Reduced drive control
• Two serial communications interfaces (SCI):
• – Full-duplex operation
• – Standard mark/space non-return-to-zero (NRZ) format
• – 13-bit baud rate selection
• – Programmable 8-bit or 9-bit data format
• – Separately enabled transmitter and receiver
• – Separate receiver and transmitter CPU interrupt requests
• – Programmable transmitter output polarity
• – Two receiver wakeup methods (idle line and address mark)
• – Interrupt-driven operation with eight flags
• – Receiver framing error detection
• – Hardware parity checking
• – 1/16 bit-time noise detection
• – General-purpose input/output port
• Two timers:
• – Four 16-bit input capture/output compare channels
• – 16-bit architecture
• – 16-bit pulse accumulator
• – Pulse widths variable from microseconds to seconds
• – Prescaler
• – Toggle-on-overflow feature for pulse-width modulator (PWM) generation
• – Timer port pullups enabled on reset
• Queued analog-to-digital converter (QADC):
• – Eight analog input channels
• – 10-bit resolution ±2 counts accuracy
• – Minimum 7 µs conversion time
• – Internal sample and hold
• – Programmable input sample time for various source impedances
• – Two conversion command queues with a total of 64 entries
• – Subqueues possible using pause mechanism
• – Queue complete and pause software interrupts available on both queues
• – Queue pointers indicate current location for each queue
• – Automated queue modes initiated by:
• External edge trigger and gated trigger
• Periodic/interval timer, within queued analog-to-digital converter (QADC) module {queue1 and queue2}
• Software command
• – Single-scan or continuous-scan of queues
• – Output data readable in three formats:
• Right-justified unsigned
• Left-justified signed
• Left-justified unsigned
• – Unused analog channels can be used as digital input/output (I/O)
• – Minimum pin set configuration implemented (Continue)

Specifications