TOSHIBA TC358771XBG

TC358771XBG General Description

Features● DSI Receiver Configurable 1- up to 4-Data-Lane DSI Link withbi-directional support on Data Lane 0 Maximum bit rate of 1 Gbps/lane Video input data formats:- RGB565 16 bits per pixel- RGB666 18 bits per pixel- RGB666 loosely packed 24 bits per pixel- RGB888 24 bits per pixel Video frame size:- Up to 1600×1200 24-bit/pixel resolution tosingle-link LVDS display panel, limited by 135 MHzLVDS speed- Up to WUXGA resolutions (1920×1200 24-bitpixels) to dual-link LVDS display panel, limited by4 Gbps DSI link speed Supports Video Stream packets for video datatransmission. Supports generic long packets for accessing thechip's register set Supports the path for Host to control the on-chipI2C Master● LVDS FPD Link Transmitter Supports single-link or dual-link Maximum pixel clock frequency of 135 MHz. Supports display up to 1600×1200 24-bit/pixelresolution for single-link, or up to 1920×120024-bit resolutions for dual-link Supports the following pixel formats:- RGB666 18 bits per pixel- RGB888 24 bits per pixel Features Toshiba Magic Square algorithm whichenables a RGB666 display panel to produce adisplay quality almost equivalent to that of anRGB888 24-bit panel Flexible mapping of parallel data input bit ordering Supports programmable clock polarity Supports two power saving states- Sleep state, when receiving DSI ULPS signaling- Standby state, entered by STBY pin assertion● Back Light Engine Provides a proper backlight parameter to theenvironment light● System Operation Host configures the chip through DSI link Through DSI link, Host accesses the chip registerset using Generic Write and Read packets. OneGeneric Long Write packet can write to multiplecontiguous register addresses Includes an I2C Master function which is controlledby Host through DSI link (multi-master is notsupported) Power management features to save power Configuration registers is also accessible throughI2C Slave interface● Clock Source LVDS pixel clock source is either from externalclock EXTCLK or derived from DSICLK. A built-in PLL generates the high-speed LVDSserializing clock requiring no external components● Digital Input/Output Signals All Digital Input signals are 3.3V tolerant All Digital Output signals can output ranging from1.8V to 3.3V depending on IO supply voltage● Power supply MIPI DSI D-PHY: 1.2 V LVDS PHY: 1.8 V I/O: 1.8 V - 3.3V (all IO supply pins mustbe same level) Digital Core: 1.2 V● Power Consumption ( Typical Condition ) Evaluation image data: color bar Power Down State is achieved by:1. Reset asserted2. EXTCLK not toggling3. STBY = 04. DSI in ULPS Drive● Packaging Information BGA64 (0.65mm ball pitch)- Supports DSI-RX 4-data-lanes + Dual-LinkLVDS-TX- 6.0mm × 6.0mm × 1.0mm BGA49 (0.65mm ball pitch)- Supports DSI-RX 4-data-lanes + Single-LinkLVDS-TX- 5.0mm × 5.0mm × 1.0mm

Specifications